1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, a method of manufacturing a MOS (metal-oxide-semiconductor) transistor.
2. Description of the Prior Art
The performance of Si semiconductor elements, in particular, MOSFETs, has increased year after year with the advance of large-scale integrated circuits (LSI). However, it has been recently pointed out that the miniaturization attained by lithographic technology has reached its limit, and that carrier mobility has almost reached theoretical mobility in Si. Under the circumstances, it is difficult to further improve the performance of MOSFETs. To attain higher performance of the semiconductor device, attempts have been made to use a strained silicon (Si) layer, which has been grown epitaxially on a Si wafer with a silicon germanium (SiGe) layer disposed therebetween, for the channel area. In this type of strained Si-FET, a biaxial tensile strain occurs in the silicon layer due to the SiGe which has a larger lattice constant than Si, and, as a result, the Si band structure alters, the degeneracy is lifted, and the carrier mobility increases. This enhances the speed performance of PMOS or NMOS devices.
Other attempts have been made to use germanium embedded in a source/drain region formed by selective epitaxial growth as a compressive strained silicon film to enhance electron mobility in a PMOS transistor. However, germanium doped into selective epitaxial silicon would damage hole mobility of a NMOS transistor. Thus, the doping of germanium into the selective epitaxial silicon during the manufacture of a PMOS device needs to be performed while NMOS devices on the same semiconductor substrate are not affected. The similar situation applies to the NMOS manufacturing. Carbon is embedded in a source/drain region formed by selective epitaxial growth as a tensile strained silicon film to enhance electron mobility in a NMOS transistor. Thus, the doping of carbon into the selective epitaxial silicon during the manufacture of NMOS devices needs to be performed while PMOS devices on the same semiconductor substrate are not affected. Thus, in a conventional technology, the NMOS/PMOS region is covered using an oxide layer as a mask during the processes of a source/drain trench pattern definition and is refilled with the selective epitaxial silicon in the manufacturing of the PMOS/NMOS devices. An etching process including dry etching and/or wet etching is used to define the source/drain trench pattern. For example, an anisotropic dry etching is performed and then an isotropic wet etching is performed to form source/drain trenches, as shown in FIG. 1. FIG. 1 shows a semiconductor substrate 10, a gate oxide layer 12, a gate 14, a spacer 16, and a cap layer 18. However, as the size for semiconductor device gets smaller, the reactants in the etching system or the ions with energy have difficulty in reaching the etching target or the products have difficulty in discharging, resulting in a reduced etching rate. This phenomenon is worsened as the etching area becomes smaller, which is called the micro loading effect. Especially when a source/drain trench pattern has both isolated and dense regions, it is difficult to accurately define the pattern as desired.
U.S. Pat. No. 6,372,583 discloses a method for making a semiconductor device. FIG. 2 briefly shows a schematic cross-sectional view at the process stage of removal of mask on the gate area. In the method, the intended source/drain region in a semiconductor substrate 10 is etched using a mask 28, an epitaxial growth process is performed to fill the first part of a trench (regions 20, 22), then an oxide is filled into the second part of the trench (regions 24, 26), and a gate is formed after the mask on the intended gate region is removed. Regions 30 are halo implanted regions. In this method, the removal of the source/drain region is attained by an anisotropic dry etching and an isotropic wet etching. Thus, this method may suffer from the micro-loading effect as described above.
Thus, a need exists to provide a method of manufacturing a MOS transistor to define the desired source/drain trench pattern in order to produce a MOS transistor with good performance.